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Rockchip GMAC-Moduskonfiguration: RGMII, RMII, SGMII und QSGMII

Vollständige GMAC-Takt-, PHY-Modus- und pinctrl-Konfigurationen für 14 Rockchip-Plattformgruppen einschließlich RK3576/RK3588.

· ArmSoM Editorial · Rockchip source documentation · 56 Min. Lesezeit

Anwendbarkeit auf ArmSoM

Dies ist eine Rockchip-Plattformreferenz, kein Testbericht zu ArmSoM-Hardware. Zur Anpassung müssen Ethernet-Schnittstelle, PHY, Versorgung, Reset, IOMUX, Referenztakte und Ziel-SDK/BSP der konkreten Platine geprüft werden. Eine Unterstützung auf jedem ArmSoM-Board wird damit nicht nachgewiesen. Es erfolgte keine Hardwareprüfung. Alle Protokolle, Durchsatzwerte und Timing-Ergebnisse sind Quellbeispiele, keine ArmSoM-Messungen.

Beide Fassungen tragen V1.4.0, mit 65 chinesischen und 68 englischen Seiten. Die 14 Plattformgruppen sind PX30, RK1808, RK3128, RK3228, RK3288, RK3328, RK3368, RK3399, RK3528, RK3562, RK3568, RK3588/RK3576, RV1108 und RV1126. Die ursprüngliche Produkttabelle nennt „alle Versionen“; das ist eine Verallgemeinerung der Quelle, kein Nachweis, dass jedes BSP oder Board diese Beispiele direkt verwenden kann. Erhaltene technische Änderungen: V1.1.0 ergänzte RK3588, V1.2.0 RK3528, V1.3.0 RK3562 und V1.4.0 RK3576 mit RK3588-Konfiguration als Referenz. Chinesisch folgt der chinesischen Quelle, Englisch/Russisch/Deutsch der englischen. Alle sechs Abbildungen stammen aus den jeweiligen Original-PDFs.

Unterschiede trotz gleicher Version bleiben erhalten: §3.4.5 verwendet phy-mode rmii auf Chinesisch, aber RMII auf Englisch; §3.10.4 lässt im Englischen Semikolons an zwei PHY-Unterknotenabschlüssen aus; §3.10.5 beendet gmac0m0 im Chinesischen mit rgmiim1_rgmii_bus, im Englischen dagegen mit rgmiim0_rgmii_bus. Diese Konfigurationen sind nicht als sofort baubar geprüft. Die Pluszeichen sind Änderungsmarkierungen der Quelle; prüfen Sie sie vor Verwendung gegen das Ziel-BSP. Technische Werte wurden nicht stillschweigend korrigiert.

Redaktionelle Hinweise · ArmSoM-Dokumentation

Produktgeltungsbereich der Quelle

Chipsatz Kernel-Version
Rockchip Alle Versionen (Verallgemeinerung der Quelle; BSP-spezifisch)

Die wichtigsten Anschlussdiagramme für RGMII/RMII sind nachfolgend aufgeführt:

1. RGMII-Modus

Bei Verwendung des Taktausgangs der Controller-PLL stellt der vom PHY gelieferte 125M-Eingangstakt eine alternative Lösung dar.

1.1 PLL-Ausgang 125M für TX_CLK, Quarz 25M für PHY

Die PLL des Hauptcontrollers liefert den für TXCLK benötigten Takt; der 25M-Takt des PHY kommt vom Quarzoszillator.

Originales Anschlussdiagramm, englisches PDF S.6

Originales Anschlussdiagramm: englisches PDF S.6.

1.2 PLL-Ausgang 125M für TX_CLK, PLL 25M für PHY

Die Controller-PLL liefert den Takt für TXCLK; auch der 25M-Takt des PHY wird vom Hauptcontroller geliefert.

Originales Anschlussdiagramm, englisches PDF S.7

Originales Anschlussdiagramm: englisches PDF S.7.

1.3 125M-TX_CLK-Eingang vom PHY, PLL 25M für PHY

Der PHY liefert den für TXCLK benötigten Takt; der Hauptcontroller liefert den 25M-Takt des PHY.

Originales Anschlussdiagramm, englisches PDF S.8

Originales Anschlussdiagramm: englisches PDF S.8.

1.4 125M-TX_CLK-Eingang vom PHY, Quarz 25M für PHY

Der PHY liefert den für TXCLK benötigten Takt; der 25M-Takt des PHY stammt vom Quarzoszillator.

Originales Anschlussdiagramm, englisches PDF S.9

Originales Anschlussdiagramm: englisches PDF S.9.

2. RMII-Modus

2.1 RMII-Taktausgang

Der Controller liefert den für RMII benötigten Takt.

Originales Anschlussdiagramm, englisches PDF S.10

Originales Anschlussdiagramm: englisches PDF S.10.

2.2 RMII-Takteingang

Der PHY liefert den für RMII benötigten Takt.

Originales Anschlussdiagramm, englisches PDF S.11

Originales Anschlussdiagramm: englisches PDF S.11.

Auch im RMII-Modus kann der Quarz durch einen 25M-Ausgang des Hauptcontrollers ersetzt werden.

3. Moduskonfiguration

Die Konfiguration der verschiedenen Modi umfasst hauptsächlich PHY-Modus, Takt und pinctrl. Diese Einstellungen hängen zusammen und müssen gleichzeitig angepasst werden, andernfalls funktioniert die Schnittstelle nicht korrekt. Nachfolgend stehen Referenzen für verschiedene Konfigurationen unterschiedlicher Chips anhand der Board-DTS des SDK. Im Mittelpunkt stehen die mit „+“ markierten Änderungen im gmac-Knoten des DTS.

3.1 PX30

3.1.1 PX30 RMII Taktausgang

&gmac {
      phy-supply = <&vcc_phy>;
+     clock_in_out = "output";

+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-rates = <50000000>;
      snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 50000 50000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
      status = "okay";
};

3.1.2 PX30 RMII Takteingang

&gmac {
      phy-supply = <&vcc_phy>;
+     clock_in_out = "input";

+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-parents = <&gmac_clkin>;
      snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 50000 50000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins &mac_refclk>;
      status = "okay";
};

3.2 RK1808

3.2.1 RK1808 RMII Taktausgang

&gmac {
      phy-supply = <&vcc_phy>;

+     phy-mode = "rmii";
+     clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
+            <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>,
+            <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>,
+            <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII_SPEED>;
+     clock-names = "stmmaceth", "mac_clk_rx",
+                "mac_clk_tx", "clk_mac_ref",
+                "clk_mac_refout", "aclk_mac",
+                "pclk_mac", "clk_mac_speed";
+     assigned-clocks = <&cru SCLK_GMAC_RX_TX>;

+     assigned-clock-parents = <&cru SCLK_GMAC_RMII_SPEED>;
      snps,reset-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 50000 50000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      status = "okay";
};

3.2.2 RK1808 RMII Takteingang

+&gmac_clkin {
+     clock-frequency = <50000000>;
+};


&gmac {
      phy-supply = <&vcc_phy>;
      phy-mode = "rmii";
+     clock_in_out = "input";
+     clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
+            <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>,
+            <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>,
+            <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII_SPEED>;
+     clock-names = "stmmaceth", "mac_clk_rx",
+                "mac_clk_tx", "clk_mac_ref",
+                "clk_mac_refout", "aclk_mac",
+                "pclk_mac", "clk_mac_speed";

+     assigned-clocks = <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC>;
+     assigned-clock-parents = <&cru SCLK_GMAC_RMII_SPEED>, <&gmac_clkin>;
      snps,reset-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 50000 50000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      status = "okay";
};

3.2.3 RK1808 RGMII Taktausgang

&gmac {
      phy-supply = <&vcc_phy>;

+     phy-mode = "rgmii";
+     clock_in_out = "output";
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-rates = <125000000>;
      snps,reset-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

      tx_delay = <0x50>;
      rx_delay = <0x3a>;
      status = "okay";
};

3.2.4 RK1808 RGMII Takteingang

&gmac {
      phy-supply = <&vcc_phy>;
+     phy-mode = "rgmii";

+     clock_in_out = "input";
+     assigned-clocks = <&cru SCLK_GMAC>;
+     assigned-clock-parents = <&gmac_clkin>;
      snps,reset-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;
      tx_delay = <0x50>;
      rx_delay = <0x3a>;
      status = "okay";
};

3.3 RK3128

3.3.1 RK3128 RMII Taktausgang

&gmac {
+     assigned-clocks = <&cru SCLK_MAC_SRC>;

+     assigned-clock-rates = <50000000>;
+     clock_in_out = "output";
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";
      snps,reset-active-low;
      snps,reset-delays-us = <0 10000 50000>;
      snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
      status = "okay";
};

3.3.2 RK3128 RMII Takteingang

+&clkin_gmac {
+     clock-frequency = <50000000>;
+};


&gmac {
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-parents = <&clkin_gmac>;
+     clock_in_out = "input";
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";
      snps,reset-active-low;
      snps,reset-delays-us = <0 10000 50000>;
      snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;

      status = "okay";
};

3.3.3 RK3128 RGMII Takteingang

&gmac {
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-parents = <&clkin_gmac>;

+     clock_in_out = "input";
+     pinctrl-names = "default";
+     pinctrl-0 = <&rgmii_pins>;
      phy-supply = <&vcc_phy>;
+     phy-mode = "rgmii";
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
      snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
      tx_delay = <0x30>;
      rx_delay = <0x16>;
      status = "okay";
};

3.4 RK3228

3.4.1 RK3228 RMII Taktausgang

&gmac {
+     assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;

+     assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+     assigned-clock-rates = <0>, <50000000>;
+     clock_in_out = "output";
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";

+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
      status = "okay";
};

3.4.2 RK3228 RMII Takteingang

+&ext_gmac: external-gmac-clock {
+     clock-frequency = <50000000>;
+}


&gmac {
+     assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
+     assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+     clock_in_out = "input";
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;

      status = "okay";
};

3.4.3 RK3228 RGMII Taktausgang

&gmac {
+     assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
+     assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;

+     assigned-clock-rates = <0>, <125000000>;
+     clock_in_out = "output";
      phy-supply = <&vcc_phy>;
+     phy-mode = "rgmii";
+     pinctrl-names = "default";
+     pinctrl-0 = <&rgmii_pins>;
      snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
      tx_delay = <0x30>;
      rx_delay = <0x10>;
      status = "okay";
};

3.4.4 RK3228 RGMII Takteingang

&gmac {
+     assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;

+     assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+     clock_in_out = "input";
      phy-supply = <&vcc_phy>;
+     phy-mode = "rgmii";
+     pinctrl-names = "default";
+     pinctrl-0 = <&rgmii_pins>;
      snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
      tx_delay = <0x30>;
      rx_delay = <0x10>;
      status = "okay";

};

3.4.5 RK3228 Interner EPHY

&gmac {
+     assigned-clocks = <&cru SCLK_MAC_SRC>;
+     assigned-clock-rates = <50000000>;

+     clock_in_out = "output";
      phy-supply = <&vcc_phy>;
+     phy-mode = "RMII";
      phy-handle = <&phy>;
      status = "okay";

      mdio {
           compatible = "snps,dwmac-mdio";
           #address-cells = <1>;
           #size-cells = <0>;

           phy: ethernet-phy@0 {

                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
                 reg = <0>;
                 clocks = <&cru SCLK_MAC_PHY>;
                 resets = <&cru SRST_MACPHY>;
                 phy-is-integrated;
           };
      };
};

3.5 RK3288

3.5.1 RK3288 RMII Taktausgang

&gmac {
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";

+     clock_in_out = "output";
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-rates = <50000000>;
      snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 1000000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      status = "okay";
};

3.5.2 RK3288 RMII Takteingang

+&ext_gmac: external-gmac-clock {
+     clock-frequency = <50000000>;
+}


&gmac {
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";
+     clock_in_out = "input";
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-parents = <&ext_gmac>;
      snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 1000000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;

      status = "okay";
};

3.5.3 RK3288 RGMII Takteingang

&gmac {
      phy-supply = <&vcc_phy>;
+     phy-mode = "rgmii";

+     clock_in_out = "input";
      snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 1000000>;
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-parents = <&ext_gmac>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&rgmii_pins>;
      tx_delay = <0x30>;
      rx_delay = <0x10>;
      status = "okay";
};

3.6 RK3328

3.6.1 RK3328 RMII Taktausgang

&gmac2io {
      phy-supply = <&vcc_phy>;

+     phy-mode = "rmii";
+     clock_in_out = "output";
+     assigned-clocks = <&cru SCLK_MAC2IO>;
+     assigned-clock-rates = <50000000>;
      snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmiim1_pins>;
      status = "okay";
};

3.6.2 RK3328 RMII Takteingang

+&clkin_gmac {
+     clock-frequency = <50000000>;

+};

&gmac2io {
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";
+     clock_in_out = "input";
+     assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+     assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
      snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmiim1_pins>;

      status = "okay";
};

3.6.3 RK3328 RGMII Takteingang

&gmac2io {
      phy-supply = <&vcc_phy>;
+     phy-mode = "rgmii";

+     clock_in_out = "input";
+     assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+     assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
      snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rgmiim1_pins>;
      tx_delay = <0x26>;
      rx_delay = <0x11>;
      status = "okay";
};

3.6.4 RK3328 Interner EPHY

&gmac2phy {
      phy-supply = <&vcc_phy>;

+     clock_in_out = "output";
+     assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+     assigned-clock-rate = <50000000>;
+     assigned-clocks = <&cru SCLK_MAC2PHY>;
+     assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
      status = "okay";
};

3.7 RK3368

3.7.1 RK3368 RMII Taktausgang

&gmac {
      phy-supply = <&vcc_lan>;

+     phy-mode = "rmii";
+     clock_in_out = "output";
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-rates = <50000000>;
      snps,reset-gpio = <&gpio3 12 0>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      status = "ok";
};

3.7.2 RK3368 RMII Takteingang

+&ext_gmac {
+     clock-frequency = <50000000>;

+}

&gmac {
      phy-supply = <&vcc_lan>;
+     phy-mode = "rmii";
+     clock_in_out = "input";
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-parents = <&ext_gmac>;
      snps,reset-gpio = <&gpio3 12 0>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";

+     pinctrl-0 = <&rmii_pins>;
      status = "ok";
};

3.7.3 RK3368 RGMII Takteingang

&gmac {
      phy-supply = <&vcc_lan>;

+     phy-mode = "rmii";
+     clock_in_out = "input";
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-parents = <&ext_gmac>;
      snps,reset-gpio = <&gpio3 12 0>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      status = "okay";
};

3.8 RK3399

3.8.1 RK3399 RMII Taktausgang

&gmac {
+     assigned-clocks = <&cru SCLK_MAC>;

+     assigned-clock-rates = <50000000>;
+     clock_in_out = "output";
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";

+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
      status = "okay";
};

3.8.2 RK3399 RMII Takteingang

+&clkin_gmac {
+     clock-frequency = <50000000>;
+};


&gmac {
+     assigned-clocks = <&cru SCLK_RMII_SRC>;
+     assigned-clock-parents = <&clkin_gmac>;
+     clock_in_out = "input";
      phy-supply = <&vcc_phy>;
+     phy-mode = "rmii";
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;

      status = "okay";
};

3.8.3 RK3399 RGMII Takteingang

&gmac {
+     assigned-clocks = <&cru SCLK_RMII_SRC>;
+     assigned-clock-parents = <&clkin_gmac>;

+     clock_in_out = "input";
      phy-supply = <&vcc_phy>;
+     phy-mode = "rgmii";
+     pinctrl-names = "default";
+     pinctrl-0 = <&rgmii_pins>;
      snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
      tx_delay = <0x28>;
      rx_delay = <0x11>;
      status = "okay";
};

3.9 RK3528

3.9.1 GMAC1 RMII 50M-Taktausgang, PLL-Ausgang 25M

&gmac1 {
   phy-mode = "rmii";
   clock_in_out = "output";


   snps,reset-gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   snps,reset-delays-us = <0 10000 50000>;

   pinctrl-names = "default";
   pinctrl-0 = <&rgmii_miim
         &rgmii_tx_bus2
         &rgmii_rx_bus2
         &rgmii_clk
         &eth_pins>;

   phy-handle = <&rmii1_phy>;

   status = "okay";
};

&mdio1 {
   rmii1_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      clocks = <&cru CLK_GMAC1_VPU_25M>;
   };
};

3.9.2 GMAC1 RMII 50M-Takteingang, PLL-Ausgang 25M

&gmac1 {
   phy-mode = "rmii";

   clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   snps,reset-delays-us = <0 10000 50000>;

   pinctrl-names = "default";
   pinctrl-0 = <&rgmii_miim
         &rgmii_tx_bus2
         &rgmii_rx_bus2
         &rgmii_clk
         &eth_pins>;
   phy-handle = <&rmii1_phy>;
   status = "okay";
};


&mdio1 {
   rmii1_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      clocks = <&cru CLK_GMAC1_VPU_25M>;
   };
};

3.9.3 GMAC1 RGMII PLL-Ausgang 25M für PHY, PLL-Ausgang 125M für TX_CLK

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "output";

   snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x30>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmii_miim
         &rgmii_tx_bus2

         &rgmii_rx_bus2
         &rgmii_rgmii_clk
         &rgmii_rgmii_bus
         &eth_pins>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio1 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";

      reg = <0x1>;
      clocks = <&cru CLK_GMAC1_VPU_25M>;
   };
};

3.9.4 GMAC1 RGMII Quarz 25M für PHY, PLL-Ausgang 125M für TX_CLK

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "output";

   snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x30>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmii_miim

         &rgmii_tx_bus2
         &rgmii_rx_bus2
         &rgmii_rgmii_clk
         &rgmii_rgmii_bus>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio1 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;

   };
};

3.9.5 GMAC1 RGMII PLL-Ausgang 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */

   phy-mode = "rgmii-rxid";
   clock_in_out = "input";

   snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x30>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmii_miim
            &rgmii_tx_bus2
            &rgmii_rx_bus2
            &rgmii_rgmii_clk

            &rgmii_rgmii_bus
            &rgmii_clk
            &eth_pins>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio1 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;

      clocks = <&cru CLK_GMAC1_VPU_25M>;
   };
};

3.9.6 GMAC1 RGMII Quarz 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "input";

   snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x30>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmii_miim
         &rgmii_tx_bus2

         &rgmii_rx_bus2
         &rgmii_rgmii_clk
         &rgmii_rgmii_bus
         &rgmii_clk>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio1 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";

      reg = <0x1>;
   };
};

3.9.7 GMAC0 & FEPHY

GMAC0 ist intern mit FEPHY verbunden und fest auf RMII eingestellt; andere Modi sind nicht konfigurierbar. Die PHY-LED-Funktion kann jedoch entsprechend dem Schaltplan eingestellt werden. Es gibt 3 Funktions-IOs, die über den jeweiligen IO-IOMUX konfiguriert werden; die Standardkonfiguration lautet:

&rmii0_phy {
   pinctrl-names = "default";
   pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>;

};

3.10 RK3562

3.10.1 RK3562 RMII Taktausgang

gmac0m0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */

   phy-mode = "rmii";
   clock_in_out = "output";

   snps,reset-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim0_miim
         &rgmiim0_tx_bus2
         &rgmiim0_rx_bus2
         &rgmiim0_clk>;


   phy-handle = <&rmii_phy>;
   status = "okay";
};

&mdio0 {
   rmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
   };
};

gmac0m1:

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rmii";

   clock_in_out = "output";

   snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim1_miim
         &rgmiim1_tx_bus2
         &rgmiim1_rx_bus2
         &rgmiim1_clk>;


   phy-handle = <&rmii_phy>;
   status = "okay";
};

&mdio0 {
   rmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
   };
};

gmac1(MAC100):

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */

   phy-mode = "rmii";
   clock_in_out = "output";

   snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   pinctrl-names = "default";
   pinctrl-0 = <&rmii_pins>;

   phy-handle = <&rmii_phy>;

   status = "okay";
};

&mdio1 {
   rmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
   };
};

3.10.2 RMII Takteingang, PLL-Ausgang 25M für PHY

gmac0m0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rmii";

   clock_in_out = "input";

   snps,reset-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim0_miim
         &rgmiim0_tx_bus2
         &rgmiim0_rx_bus2
         &rgmiim0_clk
         &ethm0_pins>;


   phy-handle = <&rmii_phy>;
   status = "okay";
};

&mdio0 {
   rmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clock-rates = <25000000>;

   };
};

gmac0m1:

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rmii";

   clock_in_out = "input";

   snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim1_miim
         &rgmiim1_tx_bus2
         &rgmiim1_rx_bus2
         &rgmiim1_clk
         &ethm1_pins>;


   phy-handle = <&rmii_phy>;
   status = "okay";
};

&mdio0 {
   rmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clock-rates = <25000000>;
   };

};

gmac1(MAC100):

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */

   phy-mode = "rmii";
   clock_in_out = "input";

   snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   pinctrl-names = "default";
   pinctrl-0 = <&rmii_pins
         &ethm1_pins>;

   phy-handle = <&rmii_phy>;

   status = "okay";
};

&mdio1 {
   rmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clock-rates = <25000000>;
   };
};

3.10.3 RGMII PLL-Ausgang 25M für PHY, PLL-Ausgang 125M für TX_CLK

gmac0m0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "output";

   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x3f>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim0_miim
            &rgmiim0_tx_bus2

            &rgmiim0_rx_bus2
            &rgmiim0_rgmii_clk
            &rgmiim0_rgmii_bus
            &ethm0_pins>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio0 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";

      reg = <0x1>;
      clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clock-rates = <25000000>;
   };
};

gmac0m1

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "output";

   snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;
   tx_delay = <0x3f>;
   /* rx_delay = <0x3f>; */


   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim1_miim
            &rgmiim1_tx_bus2
            &rgmiim1_rx_bus2
            &rgmiim1_rgmii_clk
            &rgmiim1_rgmii_bus
            &ethm1_pins>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};


&mdio0 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clock-rates = <25000000>;
   };
};

3.10.4 RGMII PLL-Ausgang 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

gmac0m0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x3f>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim0_miim

            &rgmiim0_tx_bus2
            &rgmiim0_rx_bus2
            &rgmiim0_rgmii_clk
            &rgmiim0_rgmii_bus
            &rgmiim0_clk
            &ethm0_pins>;
   phy-handle = <&rgmii_phy>;
   status = "okay";
};


&mdio0 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clock-rates = <25000000>;
   }
};

gmac0m1

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */

   phy-mode = "rgmii-rxid";
   clock_in_out = "input";

   snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x39>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim1_miim

            &rgmiim1_tx_bus2
            &rgmiim1_rx_bus2
            &rgmiim1_rgmii_clk
            &rgmiim1_rgmii_bus
            &rgmiim1_clk
            &ethm1_pins>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio0 {

   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
      assigned-clock-rates = <25000000>;
   }
};

3.10.5 RGMII Quarz 25M für PHY, PLL-Ausgang 125M für TX_CLK

gmac0m0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "output";

   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x3f>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim0_miim
         &rgmiim0_tx_bus2

         &rgmiim0_rx_bus2
         &rgmiim0_rgmii_clk
         &rgmiim0_rgmii_bus>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio0 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;

   };
};

gmac0m1

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "output";

   snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x3f>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim1_miim
         &rgmiim1_tx_bus2
         &rgmiim1_rx_bus2

         &rgmiim1_rgmii_clk
         &rgmiim1_rgmii_bus>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio0 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
   };

};

3.10.6 RGMII Quarz 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

gmac0m0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x3f>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim0_miim

            &rgmiim0_tx_bus2
            &rgmiim0_rx_bus2
            &rgmiim0_rgmii_clk
            &rgmiim0_rgmii_bus
            &rgmiim0_clk>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio0 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";

      reg = <0x1>;
   };
};

gmac0m1

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   phy-mode = "rgmii-rxid";

   clock_in_out = "input";

   snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   tx_delay = <0x39>;
   /* rx_delay = <0x3f>; */

   pinctrl-names = "default";
   pinctrl-0 = <&rgmiim1_miim
            &rgmiim1_tx_bus2

            &rgmiim1_rx_bus2
            &rgmiim1_rgmii_clk
            &rgmiim1_rgmii_bus
            &rgmiim1_clk>;

   phy-handle = <&rgmii_phy>;
   status = "okay";
};

&mdio0 {
   rgmii_phy: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";

      reg = <0x1>;
   };
};

3.11 RK3568

3.11.1 RK3568 RMII Taktausgang

gmac0

&gmac0 {
+     phy-mode = "rmii";

+     clock_in_out = "output";
+     assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+     assigned-clock-parents = <&cru SCLK_GMAC0_RMII_SPEED>;
+     assigned-clock-rates = <0>, <50000000>;
      snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;

      pinctrl-names = "default";
      pinctrl-0 = <&gmac0_miim &gmac0_clkinout &gmac0_rx_bus2 &gmac0_tx_bus2>;

      phy-handle = <&rmii_phy0>;
      status = "okay";
};

&mdio0 {
      rmii_phy0: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };

};

gmac1m0:

&gmac1 {
+     phy-mode = "rmii";

+     clock_in_out = "output";
+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RMII_SPEED>;
+     assigned-clock-rates = <0>, <50000000>;

      snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m0_miim &gmac1m0_clkinout &gmac1m0_rx_bus2 &gmac1m0_tx_bus2>;

      phy-handle = <&rmii_phy1>;

      status = "okay";
};

&mdio1 {
      rmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };
};

gmac1m1:

&gmac1 {
+     phy-mode = "rmii";

+     clock_in_out = "output";
+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RMII_SPEED>;
+     assigned-clock-rates = <0>, <50000000>;
      snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;

      snps,reset-delays-us = <0 20000 100000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m1_miim &gmac1m1_clkinout &gmac1m1_rx_bus2 &gmac1m1_tx_bus2>;

      phy-handle = <&rmii_phy1>;
      status = "okay";
};

&mdio1 {
      rmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";

           reg = <0x0>;
      };
};

3.11.2 RK3568 RMII Takteingang

gmac0

+&gmac0_clkin{
+     clock-frequency = <50000000>;

+};

&gmac0 {
+     phy-mode = "rmii";
+     clock_in_out = "input";

      snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;

+     assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+     assigned-clock-parents = <&cru SCLK_GMAC0_RMII_SPEED>, <&gmac0_clkin>;


+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac0_miim &gmac0_clkinout &gmac0_rx_bus2 &gmac0_tx_bus2>;

      phy-handle = <&rmii_phy0>;
      status = "okay";
};

&mdio0 {
      rmii_phy0: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };

};

gmac1m0:

+&gmac1_clkin{
+     clock-frequency = <50000000>;
+};


&gmac1 {
+     phy-mode = "rmii";
+     clock_in_out = "input";

      snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RMII_SPEED>, <&gmac1_clkin>;

+     pinctrl-names = "default";

+     pinctrl-0 = <&gmac1m0_miim &gmac1m0_clkinout &gmac1m0_rx_bus2 &gmac1m0_tx_bus2>;

      phy-handle = <&rmii_phy1>;
      status = "okay";
};
&mdio1 {
      rmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };
};

gmac1m1:

+&gmac1_clkin{
+     clock-frequency = <50000000>;

+};

&gmac1 {
+     phy-mode = "rmii";
+     clock_in_out = "input";

      snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RMII_SPEED>, <&gmac1_clkin>;

+     pinctrl-names = "default";

+     pinctrl-0 = <&gmac1m1_miim &gmac1m1_clkinout &gmac1m1_rx_bus2 &gmac1m1_tx_bus2>;

      phy-handle = <&rmii_phy1>;
      status = "okay";
};
&mdio1 {
      rmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";

           reg = <0x0>;
      };
};

3.11.3 RGMII PLL-Ausgang 25M für PHY, PLL-Ausgang 125M für TX_CLK

gmac0

&gmac0 {
+     phy-mode = "rgmii";
+     clock_in_out = "output";

+     assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
+     assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+     assigned-clock-rates = <0>, <125000000>, <25000000>;

      snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac0_miim
+               &gmac0_tx_bus2

+               &gmac0_rx_bus2
+               &gmac0_rgmii_clk
+               &gmac0_rgmii_bus
+               &eth0_pins>;

      tx_delay = <0x3c>;
      rx_delay = <0x2f>;
      phy-handle = <&rgmii_phy0>;
      status = "okay";
};

&mdio0 {
      rgmii_phy0: phy@0 {

           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
+           clocks = <&cru CLK_MAC0_OUT>;
      };
};

gmac1m0

&gmac1 {
+     phy-mode = "rgmii";

+     clock_in_out = "output";
      snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;

      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+     assigned-clock-rates = <0>, <125000000>, <25000000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m0_miim
+               &gmac1m0_tx_bus2
+               &gmac1m0_rx_bus2
+               &gmac1m0_rgmii_clk

+               &gmac1m0_rgmii_bus
+               &eth1m0_pins>;

      tx_delay = <0x4f>;
      rx_delay = <0x26>;

      phy-handle = <&rgmii_phy1>;
      status = "okay";
};

&mdio1 {
      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";

           reg = <0x0>;
+           clocks = <&cru CLK_MAC1_OUT>;
      };
};

gmac1m1

&gmac1 {
+     phy-mode = "rgmii";
+     clock_in_out = "output";


      snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+     assigned-clock-rates = <0>, <125000000>, <25000000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m1_miim

+               &gmac1m1_tx_bus2
+               &gmac1m1_rx_bus2
+               &gmac1m1_rgmii_clk
+               &gmac1m1_rgmii_bus
+               &eth1m1_pins>;


      tx_delay = <0x4f>;
      rx_delay = <0x26>;

      phy-handle = <&rgmii_phy1>;
      status = "okay";
};

&mdio1 {
      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
+           clocks = <&cru CLK_MAC1_OUT>;

      };
};

3.11.4 RGMII PLL-Ausgang 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

gmac0

&gmac0 {
+     phy-mode = "rgmii";
+     clock_in_out = "input";

+     assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
+     assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
+     assigned-clock-rates = <0>, <125000000>, <25000000>;

      snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac0_miim
+               &gmac0_tx_bus2

+               &gmac0_rx_bus2
+               &gmac0_rgmii_clk
+               &gmac0_rgmii_bus
+               &eth0_pins
+               &gmac0_clkinout>;

      tx_delay = <0x3c>;
      rx_delay = <0x2f>;
      phy-handle = <&rgmii_phy0>;
      status = "okay";
};

&mdio0 {

      rgmii_phy0: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
+           clocks = <&cru CLK_MAC0_OUT>;

      };
};

gmac1m0

&gmac1 {
+     phy-mode = "rgmii";

+     clock_in_out = "input";

      snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+     assigned-clock-rates = <0>, <125000000>, <25000000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m0_miim

+               &gmac1m0_tx_bus2
+               &gmac1m0_rx_bus2
+               &gmac1m0_rgmii_clk
+               &gmac1m0_rgmii_bus
+               &eth1m0_pins
+               &gmac1m0_clkinout>;

      tx_delay = <0x4f>;
      rx_delay = <0x26>;

      phy-handle = <&rgmii_phy1>;
      status = "okay";

};

&mdio0 {
      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
+           clocks = <&cru CLK_MAC0_OUT>;
      };
};

gmac1m1

&gmac1 {
+     phy-mode = "rgmii";

+     clock_in_out = "input";

      snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;


+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+     assigned-clock-rates = <0>, <125000000>, <25000000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m1_miim
+               &gmac1m1_tx_bus2
+               &gmac1m1_rx_bus2
+               &gmac1m1_rgmii_clk
+               &gmac1m1_rgmii_bus
+               &eth1m1_pins

+               &gmac1m1_clkinout>;

      tx_delay = <0x4f>;
      rx_delay = <0x26>;

      phy-handle = <&rgmii_phy1>;
      status = "okay";
};

&mdio1 {
      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;

+           clocks = <&cru CLK_MAC1_OUT>;
      };
};

3.11.5 RGMII Quarz 25M für PHY, PLL-Ausgang 125M für TX_CLK

gmac0

&gmac0 {
+     phy-mode = "rgmii";
+     clock_in_out = "output";

+     assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+     assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+     assigned-clock-rates = <0>, <125000000>;

      snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac0_miim
+               &gmac0_tx_bus2
+               &gmac0_rx_bus2
+               &gmac0_rgmii_clk
+               &gmac0_rgmii_bus>;


      tx_delay = <0x3c>;
      rx_delay = <0x2f>;
      phy-handle = <&rgmii_phy0>;
      status = "okay";
};

&mdio0 {
      rgmii_phy0: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };

};

gmac1m0

&gmac1 {
+     phy-mode = "rgmii";

+     clock_in_out = "output";

      snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+     assigned-clock-rates = <0>, <125000000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m0_miim

+               &gmac1m0_tx_bus2
+               &gmac1m0_rx_bus2
+               &gmac1m0_rgmii_clk
+               &gmac1m0_rgmii_bus>;

      tx_delay = <0x4f>;
      rx_delay = <0x26>;

      phy-handle = <&rgmii_phy1>;
      status = "okay";
};


&mdio1 {
      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };
};

gmac1m1

&gmac1 {
+     phy-mode = "rgmii";
+     clock_in_out = "output";


      snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+     assigned-clock-rates = <0>, <125000000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m1_miim

+               &gmac1m1_tx_bus2
+               &gmac1m1_rx_bus2
+               &gmac1m1_rgmii_clk
+               &gmac1m1_rgmii_bus>;

      tx_delay = <0x4f>;
      rx_delay = <0x26>;

      phy-handle = <&rgmii_phy1>;
      status = "okay";
};

&mdio1 {

      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };
};

3.11.6 RGMII Quarz 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

gmac0

&gmac0 {
+     phy-mode = "rgmii";

+     clock_in_out = "input";
+     assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+     assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
+     assigned-clock-rates = <0>, <125000000>;

      snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac0_miim

+               &gmac0_tx_bus2
+               &gmac0_rx_bus2
+               &gmac0_rgmii_clk
+               &gmac0_rgmii_bus
+               &gmac0_clkinout>;

      tx_delay = <0x3c>;
      rx_delay = <0x2f>;
      phy-handle = <&rgmii_phy0>;
      status = "okay";
};


&mdio0 {
      rgmii_phy0: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };
};

gmac1m0

&gmac1 {
+     phy-mode = "rgmii";
+     clock_in_out = "input";


      snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+     assigned-clock-rates = <0>, <125000000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m0_miim

+               &gmac1m0_tx_bus2
+               &gmac1m0_rx_bus2
+               &gmac1m0_rgmii_clk
+               &gmac1m0_rgmii_bus
+               &gmac1m0_clkinout>;

      tx_delay = <0x4f>;
      rx_delay = <0x26>;

      phy-handle = <&rgmii_phy1>;
      status = "okay";
};


&mdio1 {
      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;

      };
};

gmac1m1

&gmac1 {
+     phy-mode = "rgmii";

+     clock_in_out = "input";

      snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      /* Reset time is 20ms, 100ms for rtl8211f */
      snps,reset-delays-us = <0 20000 100000>;

+     assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+     assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+     assigned-clock-rates = <0>, <125000000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1m1_miim

+               &gmac1m1_tx_bus2
+               &gmac1m1_rx_bus2
+               &gmac1m1_rgmii_clk
+               &gmac1m1_rgmii_bus
+               &gmac1m1_clkinout>;

      tx_delay = <0x4f>;
      rx_delay = <0x26>;

      phy-handle = <&rgmii_phy1>;
      status = "okay";
};


&mdio1 {
      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x0>;
      };
};

3.11.7 SGMII

Zusätzlich zu den gmac- und mac-phy-Knoten müssen im DTS auch die xpcs- und combophy-Knoten konfiguriert werden.

combophy

Die Eigenschaft rockchip,sgmii-mac-sel gibt an, welcher gmac verwendet wird:

&combphy1_usq {
+     rockchip,sgmii-mac-sel = <0>; /* Use gmac0 for sgmii */
      status = "okay";

};

xpcs

&xpcs {
      status = "okay";
};

gmac0

&gmac0 {
      phy-mode = "sgmii";


      rockchip,pipegrf = <&pipegrf>;
      rockchip,xpcs = <&xpcs>;

      snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;

      assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
      assigned-clock-parents = <&gmac0_xpcsclk>;

      pinctrl-names = "default";
      pinctrl-0 = <&gmac0_miim>;


      power-domains = <&power RK3568_PD_PIPE>;
      phys = <&combphy1_usq PHY_TYPE_SGMII>;
      phy-handle = <&sgmii_phy>;
      status = "okay";
};

&mdio0 {
      sgmii_phy: phy@1 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x1>;
      };
};

gmac1

&gmac1 {
      phy-mode = "sgmii";


      rockchip,pipegrf = <&pipegrf>;
      rockchip,xpcs = <&xpcs>;

      snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;


      assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
      assigned-clock-parents = <&gmac1_xpcsclk>;

      pinctrl-names = "default";
      pinctrl-0 = <&gmac1_miim>;

      power-domains = <&power RK3568_PD_PIPE>;
      phys = <&combphy1_usq PHY_TYPE_SGMII>;
      phy-handle = <&sgmii_phy>;
      status = "okay";
};


&mdio1 {
      sgmii_phy: phy@1 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x1>;
      };
};

3.11.8 QSGMII

Wie bei SGMIIL (Schreibweise der Quelle) müssen im DTS zusätzlich zu den gmac- und mac-phy-Knoten auch xpcs und combophy konfiguriert werden.

combophy

&combphy2_psq {
   status = "okay";
};

xpcs

&xpcs {
   status = "okay";
};

&gmac0 {
   phy-supply = <&pcie20_3v3>;
   phy-mode = "qsgmii";

   rockchip,xpcs = <&xpcs>;

   snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   snps,reset-delays-us = <0 20000 100000>;

   assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
   assigned-clock-parents = <&gmac0_xpcsclk>;
   pinctrl-names = "default";
   pinctrl-0 = <&gmac0_miim>;


   power-domains = <&power RK3568_PD_PIPE>;
   phys = <&combphy2_psq PHY_TYPE_QSGMII>;
   phy-handle = <&qsgmii_phy0>;

   status = "okay";
};

&gmac1 {
   phy-supply = <&pcie20_3v3>;
   phy-mode = "qsgmii";


   assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
   assigned-clock-parents = <&gmac1_xpcsclk>;

   power-domains = <&power RK3568_PD_PIPE>;
   phy-handle = <&qsgmii_phy1>;

   status = "okay";
};

&mdio0 {
   qsgmii_phy0: phy@0 {
      compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;

   };
   qsgmii_phy1: phy@1 {
      compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
   };
   qsgmii_phy2: phy@2 {
      compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";
      reg = <0x2>;
   };
   qsgmii_phy3: phy@3 {
      compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";
      reg = <0x3>;

   };
};

3.12 RK3588/RK3576

3.12.1 RK3588/RK3576 RMII Taktausgang

gmac0

&gmac0 {
+     phy-mode = "rmii";
+     clock_in_out = "output";


     snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
     snps,reset-active-low;
     /* Reset time is 20ms, 100ms for rtl8211f */
     snps,reset-delays-us = <0 20000 100000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac0_miim
+              &gmac0_tx_bus2
+              &gmac0_rx_bus2
+              &gmac0_clkinout>;

     phy-handle = <&rmii_phy0>;

     status = "okay";
};

&mdio0 {
     rmii_phy0: phy@1 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x1>;
     };
};

gmac1:

&gmac1 {
+     phy-mode = "rmii";
+     clock_in_out = "output";


     snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
     snps,reset-active-low;
     /* Reset time is 20ms, 100ms for rtl8211f */
     snps,reset-delays-us = <0 20000 100000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac1_miim
+              &gmac1_tx_bus2
+              &gmac1_rx_bus2
+              &gmac1_clkinout>;


     phy-handle = <&rmii_phy1>;
     status = "okay";
};

&mdio1 {
     rmii_phy1: phy@1 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x1>;
     };
};

3.12.2 RK3588/RK3576 RMII Takteingang

gmac0

&gmac0 {
+     phy-mode = "rmii";
+     clock_in_out = "input";


     snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
     snps,reset-active-low;
     /* Reset time is 20ms, 100ms for rtl8211f */
     snps,reset-delays-us = <0 20000 100000>;

+     pinctrl-names = "default";
+     pinctrl-0 = <&gmac0_miim
+              &gmac0_tx_bus2
+              &gmac0_rx_bus2
+              &gmac0_clkinout>;

     phy-handle = <&rmii_phy0>;

     status = "okay";
};

&mdio0 {
     rmii_phy0: phy@1 {
           compatible = "ethernet-phy-ieee802.3-c22";
           reg = <0x1>;
     };
};

gmac1:

&gmac1 {
+  phy-mode = "rmii";

+  clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  pinctrl-names = "default";
+  pinctrl-0 = <&gmac1_miim
+           &gmac1_tx_bus2
+           &gmac1_rx_bus2
+           &gmac1_clkinout>;


   phy-handle = <&rmii_phy1>;
   status = "okay";
};
&mdio1 {
   rmii_phy1: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";

      reg = <0x1>;
   };
};

3.12.3 RGMII PLL-Ausgang 25M für PHY, PLL-Ausgang 125M für TX_CLK

gmac0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   +  phy-mode = "rgmii-rxid";

   clock_in_out = "output";

   snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   +  pinctrl-names = "default";
   +  pinctrl-0 = <&gmac0_miim
   +          &gmac0_tx_bus2
   +          &gmac0_rx_bus2
   +          &gmac0_rgmii_clk

   +          &gmac0_rgmii_bus
   +          &eth0_pins>;

   tx_delay = <0x45>;
   /* rx_delay = <0x43>; */

   phy-handle = <&rgmii_phy0>;
   status = "okay";
};

&mdio0 {
   rgmii_phy0: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";

      reg = <0x1>;
      +  clocks = <&cru REFCLKO25M_ETH0_OUT>;
   };
};

gmac1

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   +  phy-mode = "rgmii-rxid";

   +  clock_in_out = "output";
   snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;

   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   +  pinctrl-names = "default";
   +  pinctrl-0 = <&gmac1_miim
   +          &gmac1_tx_bus2
   +          &gmac1_rx_bus2
   +          &gmac1_rgmii_clk
   +          &gmac1_rgmii_bus
   +          &eth1_pins>;

   tx_delay = <0x45>;

   /* rx_delay = <0x43>; */

   phy-handle = <&rgmii_phy1>;
   status = "okay";
};

&mdio1 {
   rgmii_phy1: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      +  clocks = <&cru REFCLKO25M_ETH0_OUT>;
   };
};

3.12.4 RGMII PLL-Ausgang 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

gmac0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   +  phy-mode = "rgmii-rxid";

   +  clock_in_out = "input";

   snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   +  pinctrl-names = "default";
   +  pinctrl-0 = <&gmac0_miim
   +          &gmac0_tx_bus2
   +          &gmac0_rx_bus2
   +          &gmac0_rgmii_clk
   +          &gmac0_rgmii_bus

   +          &gmac0_clkinout
   +          &eth0_pins>;
   tx_delay = <0x45>;
   /* rx_delay = <0x43>; */


   phy-handle = <&rgmii_phy0>;
   status = "okay";
};

&mdio0 {
   rgmii_phy0: phy@1 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      +  clocks = <&cru REFCLKO25M_ETH0_OUT>;
   };
};

gmac1

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   +  phy-mode = "rgmii-rxid";

   +  clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   +  pinctrl-names = "default";
   +  pinctrl-0 = <&gmac1_miim
   +          &gmac1_tx_bus2
   +          &gmac1_rx_bus2
   +          &gmac1_rgmii_clk
   +          &gmac1_rgmii_bus

   +          &gmac1_clkinout
   +          &eth1_pins>;

   tx_delay = <0x45>;
   /* rx_delay = <0x43>; */

   phy-handle = <&rgmii_phy1>;
   status = "okay";
};

&mdio1 {
   rgmii_phy1: phy@1 {

      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x1>;
      +  clocks = <&cru REFCLKO25M_ETH0_OUT>;
   };
};

3.12.5 RGMII Quarz 25M für PHY, PLL-Ausgang 125M für TX_CLK

gmac0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   +  phy-mode = "rgmii-rxid";

   +  clock_in_out = "output";

   snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   +  pinctrl-names = "default";
   +  pinctrl-0 = <&gmac0_miim
   +          &gmac0_tx_bus2
   +          &gmac0_rx_bus2
   +          &gmac0_rgmii_clk
   +          &gmac0_rgmii_bus>;


   tx_delay = <0x45>;
   /* rx_delay = <0x43>; */

   phy-handle = <&rgmii_phy0>;
   status = "okay";
};

&mdio0 {
   rgmii_phy0: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;

   };
};

gmac1

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   +  phy-mode = "rgmii-rxid";

   +  clock_in_out = "output";

   snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   +  pinctrl-names = "default";
   +  pinctrl-0 = <&gmac1_miim
   +          &gmac1_tx_bus2
   +          &gmac1_rx_bus2
   +          &gmac1_rgmii_clk
   +          &gmac1_rgmii_bus>;


   tx_delay = <0x45>;
   /* rx_delay = <0x43>; */

   phy-handle = <&rgmii_phy1>;
   status = "okay";
};

&mdio1 {
   rgmii_phy1: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;
   };

};

3.12.6 RGMII Quarz 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

gmac0

&gmac0 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   +  phy-mode = "rgmii-rxid";

   +  clock_in_out = "input";

   snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   +  pinctrl-names = "default";
   +  pinctrl-0 = <&gmac0_miim
   +          &gmac0_tx_bus2
   +          &gmac0_rx_bus2
   +          &gmac0_rgmii_clk

   +          &gmac0_rgmii_bus
   +          &gmac0_clkinout>;

   tx_delay = <0x45>;
   /* rx_delay = <0x43>; */

   phy-handle = <&rgmii_phy0>;
   status = "okay";
};

&mdio0 {
      rgmii_phy0: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";

           reg = <0x0>;
      };
};

gmac1

&gmac1 {
   /* Use rgmii-rxid mode to disable rx delay inside Soc */
   +  phy-mode = "rgmii-rxid";

   +  clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

   +  pinctrl-names = "default";
   +  pinctrl-0 = <&gmac1_miim
   +          &gmac1_tx_bus2
   +          &gmac1_rx_bus2
   +          &gmac1_rgmii_clk
   +          &gmac1_rgmii_bus

   +          &gmac1_clkinout>;

   tx_delay = <0x45>;
   /* rx_delay = <0x43>; */

   phy-handle = <&rgmii_phy1>;
   status = "okay";
};

&mdio1 {
      rgmii_phy1: phy@0 {
           compatible = "ethernet-phy-ieee802.3-c22";

           reg = <0x0>;
      };
};

3.13 RV1108

3.13.1 RV1108 RMII Takteingang

+gmac_clkin: gmac_clkin {
+     compatible = "fixed-clock";

+     clock-output-names = "gmac_clkin";
+     clock-frequency = <50000000>;
+     #clock-cells = <0>;
+};

&gmac {
+     phy-mode = "rmii";
+     clock_in_out = "input";
+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-parents = <&gmac_clkin>;

      snps,reset-gpio = <&gpio3 12 0>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      status = "ok";
};

3.13.2 RV1108 RMII Taktausgang

&gmac {
+     phy-mode = "rmii";
+     clock_in_out = "output";

+     assigned-clocks = <&cru SCLK_MAC>;
+     assigned-clock-rates = <50000000>;
      snps,reset-gpio = <&gpio3 12 0>;
      snps,reset-active-low;
      snps,reset-delays-us = <0 20000 100000>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&rmii_pins>;
      status = "ok";
};

3.14 RV1126

3.14.1 RGMII PLL-Ausgang 25M für PHY, PLL-Ausgang 125M für TX_CLK

gmac m0

&gmac {
+  phy-mode = "rgmii";
+  clock_in_out = "output";


   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru
CLK_GMAC_ETHERNET_OUT>;
+  assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RGMII_MODE_CLK>;
+  assigned-clock-rates = <125000000>, <0>, <25000000>;

+  pinctrl-names = "default";

+  pinctrl-0 = <&rgmiim0_miim &rgmiim0_bus2 &rgmiim0_bus4 &clkm0_out_ethernet>;
   tx_delay = <0x2a>;
   rx_delay = <0x1a>;


   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;
+     clocks = <&cru CLK_GMAC_ETHERNET_OUT>;
   };
};

gmac m1

&gmac {
+  phy-mode = "rgmii";
+  clock_in_out = "output";


   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru
CLK_GMAC_ETHERNET_OUT>;
+  assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
+  assigned-clock-rates = <125000000>, <0>, <25000000>;

+  pinctrl-names = "default";
+  pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clkm1_out_ethernet>;


   tx_delay = <0x2a>;
   rx_delay = <0x1a>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;

+     clocks = <&cru CLK_GMAC_ETHERNET_OUT>;
   };
};

3.14.2 RGMII PLL-Ausgang 25M für PHY, RGMII-Takteingang 125M für TX_CLK

gmac m0

&gmac {
+  phy-mode = "rgmii";
+  clock_in_out = "input";


   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru
CLK_GMAC_ETHERNET_OUT>;
+  assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RGMII_MODE_CLK>;
+  assigned-clock-rates = <125000000>, <0>, <25000000>;

+  pinctrl-names = "default";
+  pinctrl-0 = <&rgmiim0_miim &rgmiim0_bus2 &rgmiim0_bus4 &clkm0_out_ethernet>;


   tx_delay = <0x2a>;
   rx_delay = <0x1a>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;

+     clocks = <&cru CLK_GMAC_ETHERNET_OUT>;
   };
};

gmac m1

&gmac {
+  phy-mode = "rgmii";
+  clock_in_out = "input";


   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru
CLK_GMAC_ETHERNET_OUT>;
+  assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
+  assigned-clock-rates = <125000000>, <0>, <25000000>;
+  pinctrl-names = "default";
+  pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clkm1_out_ethernet>;


   tx_delay = <0x2a>;
   rx_delay = <0x1a>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;

+     clocks = <&cru CLK_GMAC_ETHERNET_OUT>;
   };
};

3.14.3 RGMII Quarz 25M für PHY, PLL-Ausgang 125M für TX_CLK

gmac m0

&gmac {
+  phy-mode = "rgmii";

+  clock_in_out = "output";

   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>;
+  assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RGMII_MODE_CLK>;
+  assigned-clock-rates = <125000000>, <0>;

+  pinctrl-names = "default";

+  pinctrl-0 = <&rgmiim0_miim &rgmiim0_bus2 &rgmiim0_bus4 &clkm0_out_ethernet>;

   tx_delay = <0x2a>;
   rx_delay = <0x1a>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;

   };
};

gmac m1

&gmac {
+  phy-mode = "rgmii";
+  clock_in_out = "output";


   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>;
+  assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
+  assigned-clock-rates = <125000000>, <0>;

+  pinctrl-names = "default";
+  pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clkm1_out_ethernet>;


   tx_delay = <0x2a>;
   rx_delay = <0x1a>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;
   };

};

3.14.4 RGMII Quarz 25M für PHY, RGMII_CLK-Eingang 125M für TX_CLK

gmac m0

&gmac {
+  phy-mode = "rgmii";
+  clock_in_out = "input";


   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  assigned-clocks = <&cru CLK_GMAC_RGMII_M0>, <&cru CLK_GMAC_SRC_M0>, <&cru CLK_GMAC_SRC>,
<&cru CLK_GMAC_TX_RX>;
+  assigned-clock-parents = <&gmac_clkin_m0>, <&cru CLK_GMAC_RGMII_M0>, <&cru
CLK_GMAC_SRC_M0>, <&cru RGMII_MODE_CLK>;


+  pinctrl-names = "default";
+  pinctrl-0 = <&rgmiim0_miim &rgmiim0_bus2 &rgmiim0_bus4>;

   tx_delay = <0x2a>;
   rx_delay = <0x1a>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {

      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;
   };
};

gmac m1

&gmac {
+  phy-mode = "rgmii";

+  clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   /* Reset time is 20ms, 100ms for rtl8211f */
   snps,reset-delays-us = <0 20000 100000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru
CLK_GMAC_ETHERNET_OUT>;
+  assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
+  assigned-clock-rates = <125000000>, <0>, <25000000>;


+  pinctrl-names = "default";
+  pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4>;

   tx_delay = <0x2a>;
   rx_delay = <0x1a>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";

      reg = <0x0>;
   };
};

3.14.5 RV1126 RMII Taktausgang

gmac m0

&gmac {
+  phy-mode = "rmii";
+  clock_in_out = "output";


   snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   snps,reset-delays-us = <0 50000 50000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC_M0>, <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>;
+  assigned-clock-rates = <0>, <50000000>;
+  assigned-clock-parents = <&cru CLK_GMAC_RGMII_M0>, <&cru CLK_GMAC_SRC_M0>, <&cru
RMII_MODE_CLK>;

+  pinctrl-names = "default";
+  pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout>;


   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;
   };
};

gmac m1

&gmac {
+  phy-mode = "rmii";
+  clock_in_out = "output";


   snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   snps,reset-delays-us = <0 50000 50000>;

+  assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>;
+  assigned-clock-rates = <0>, <50000000>;
+  assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>, <&cru
RMII_MODE_CLK>;

+  pinctrl-names = "default";
+  pinctrl-0 = <&rmiim1_miim &rgmiim1_rxer &rmiim10_bus2 &rgmiim1_mclkinout>;


   phy-handle = <&phy>;
   status = "okay";
};

&mdio {

   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;
   };
};

3.14.6 RV1126 RMII Takteingang

gmac m0

+&gmac_clkin_m0 {
+  clock-frequency = <50000000>;

+};

&gmac {
+  phy-mode = "rmii";
+  clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   snps,reset-delays-us = <0 50000 50000>;

+  assigned-clocks = <&cru CLK_GMAC_RGMII_M0>, <&cru CLK_GMAC_SRC_M0>, <&cru CLK_GMAC_SRC>,
<&cru CLK_GMAC_TX_RX>;
+  assigned-clock-rates = <0>, <0>, <50000000>;

+  assigned-clock-parents = <&gmac_clkin_m0>,<&cru CLK_GMAC_RGMII_M0>, <&cru
CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>;

+  pinctrl-names = "default";
+  pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout_level0>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {

      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;
   };
};

gmac m1

+&gmac_clkin_m1 {
+  clock-frequency = <50000000>;

+};
&gmac {
+  phy-mode = "rmii";

+  clock_in_out = "input";

   snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
   snps,reset-active-low;
   snps,reset-delays-us = <0 50000 50000>;

+  assigned-clocks = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>,
<&cru CLK_GMAC_TX_RX>;
+  assigned-clock-rates = <0>, <0>, <50000000>;
+  assigned-clock-parents = <&gmac_clkin_m1>,<&cru CLK_GMAC_RGMII_M1>, <&cru
CLK_GMAC_SRC_M1>, <&cru RMII_MODE_CLK>;


+  pinctrl-names = "default";
+  pinctrl-0 = <&rmiim1_miim &rgmiim1_rxer &rmiim1_bus2 &rgmiim1_mclkinout_level0>;

   phy-handle = <&phy>;
   status = "okay";
};

&mdio {
   phy: phy@0 {
      compatible = "ethernet-phy-ieee802.3-c22";
      reg = <0x0>;
   };
};

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